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Several Common LED Chip Packaging Technologies

Led Package is the process of assembling an integrated circuit into the final product of a chip. Simply put, it is to place the Die produced by Foundry on a substrate that plays a bearing role, lead out the pins, and then fix the package into a whole.

As a verb, "LED Package" emphasizes the process and action of placing, fixing, sealing and leading wires. As a noun, "LED package" mainly focuses on the form and category of package, chips packaging material, shell and lead, emphasizing its important role in protecting chip, enhancing electric heating performance and facilitating assembly of the whole machine.

1. The ratio of chip area to package area should approach 1: 1 as far as possible to improve the package efficiency;
2. The pins should be as short as possible to reduce delay and the distance between pins should be as far as possible to avoid mutual interference and improve performance.
3. Based on the requirement of heat dissipation, the package should be as thin as possible.

The package is mainly divided into DIP and SMD. From the aspect of structure, LED package experienced the development from the earliest package of transistor TO (such as TO-89 and TO92) to the dual-in-line package, and then the SOP (small outline package) was developed by PHILIP Company. Later, SOJ (small outline package of J - type pin), TSOP (thin small outline package), VSOP (very small outline package), SSOP (shrunk small outline package), TSSOP (thin shrunk small outline package), SOT (small outline transistor), SOIC (small outline integrated circuit) and so on were gradually derived. In terms of materials and media, including metals, ceramics and plastics, there are still numbers of metal packages for many circuits that required by high-strength working conditions, such as military and aerospace.

1. BGA package

Ball grid array, one of surface mounting packages. Ball bumps are made on the back surface of the printed substrate in an array to replace pins. LSI chips are assembled on the front surface of the printed substrate, and then sealed by molding resin or method of potting. It is also known as pad array carrier (PAC). More than 200 pins are applied here. It is a package for multi-pin LSI. The package body can also be made smaller than QFP. For example, a BGA of 360-pin with a pin center distance of 1.5mm is only 31mm square. However, a QFP of 304-pin with a pin center distance of 0.5mm is 40mm square. Moreover, BGA does not have the problem of pin deformation like QFP does. The package was developed by a company called Motorola in the United States and was first used in portable phones and other devices. In the future, it will be widely used in personal computers in the United States. Initially, the center distance of BGA pins ( bumps ) was 1.5mm and the number of pins was 225. At present, some LSI manufacturers are also developing BGA with 500 - ball. The problem with BGA is the appearance inspection after reflow soldering. It is not clear whether there is an effective method for appearance inspection. Some people think that due to the large distance between the centers of welding, the connection can be regarded as stable and functional inspection is the only way to handle appearance inspection. Motorola calls the package sealed with molding resin OMPAC, and the package sealed with potting method GPAC (see OMPAC and GPAC).

2. BQFP package

Flat four - sided package with buffer pad for pin. In one of QFP packages, protrusions (buffer pads) are provided at four corners of the package body to prevent bending deformation of pins during transportation. U.S. semiconductor manufacturers mainly use this package in circuits such as microprocessors and ASIC. The pin center distance is 0.635mm, and the number of pins ranges from 84 to 196 (see QFP).

3. butt joint pin grid array

The nickname of surface mount PGA (see surface mount PGA).

4. c - (ceramic) package

Mark indicating ceramic package. For example, CDIP represents ceramic DIP. It is often used in practice.

5. cerdip package

Ceramic dual-in-line package sealed with glass is used in ECL RAM, DSP (Digital Signal Processor) and other circuits. Cerdip with glass window used in ultraviolet erasing EPROM and microcomputer circuit with EPROM inside. The pin center distance is 2.54mm, and the number of pins ranges from 8 to 42. In Japan, this package is denoted DIP-G ( G means glass seal ).

6. cerquad package

One of the surface mount LED packages, i.e. ceramic QFP sealed is used to package logic LSI circuits such as DSP. Cerquad with window is used to package EPROM circuit. The heat dissipation property is better than that of plastic QFP, and the power of 1. 5 ~ 2 W can be allowed under the condition of natural air cooling. But the packaging cost is 3 ~ 5 times higher than that of plastic QFP. The pin center distance is 1.27mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm and other specifications. The number of pins ranges from 32 to 368. Ceramic chip carrier with pins is one of surface mount packages. The pins are led out from four sides of the package in a T - shape. Windows are used to package ultraviolet erasing EPROM and microcomputer circuits with EPROM. This package is also called QFJ, QFJ - G (see QFJ).
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